As is well known, the read mode whereby the contents of the cells of a semiconductor integrated electronic memory circuit are read is made possible by a predetermined sequence of operations known in the art as the read cycle. A read cycle begins with a memory address of data to be read being presented to the input terminals of a memory circuit. An input stage detects the switching of an address presented to these terminals, thereby to initiate a reading operation. Row and column decoding circuits then select the memory word that has been addressed.
The circuit portion arranged to read the contents of the memory cells and convert the analog data read to digital data is known as the sense or read amplifier. This amplifier usually is of the differential type and has a pair of inputs which are connected, the one to a cell of the memory matrix and the other to a reference cell. Reading is enabled by an unbalance between the loads of the matrix leg and the reference leg.
The data sensed by the sense amplifier is then output through an output buffer stage.
Each of the above phases of a reading cycle must have a preset duration consistent with the memory access times provided by the memory circuit specifications.
All of the various phases of a reading cycle are clocked by synchronization pulses derived from a single main or ATD (Address Transition Detection) pulse. The ATD pulse is generated within the memory circuit whenever a change in address is detected on the input terminals.
In general, the ATD pulse is generated by a NOR structure whose output is at a normally high logic level. Upon the occurrence of a change in logic level at even one only of the input terminals, the NOR structure switches its output to allow a terminal from which the ATD pulse is picked up to be discharged toward ground. Shown schematically in the accompanying FIG. 1 is circuitry for generating the ATD signal as provided in the prior art.
FIG. 1 shows an ATD cell or circuitry 11 comprising two N-channel MOS input transistors, indicated at M1 and M2, which are highly conductive because sized to have a high W/L ratio.
The cell 1 farther comprises a pair of inverters 11, 12, each including a CMOS complementary pair comprising a pull-up transistor and a pull-down transistor. The pull-up transistors of the inverters 11, 12 are highly resistive, and therefore little conductive, they being sized with a reduced W/L ratio.
The structure resulting from the coupling of the inverters 11 and 12 is that of a latch register 3 having outputs Q and Q#, whereof the former, Q, is at a normally high logic level.
The latch 3 is input a signal AX and the corresponding negated signal AX.sub.-- N, through one of said input terminals, as smoothed by means of capacitors C1 and C2. These signals are enabled to pass on to the latch 3 by the respective NMOS transistors M1 and M2.
During the wait phase, only one of the input signals will be at a high logic value, e.g., AX.sub.-- N. The capacitor C2 will be discharged, while the capacitor C1 can be charged by the pull-up of the first inverter 11.
Upon the occurrence of an input transition, the capacitor C1 of the transistor M1 is discharged rapidly, while the capacitor C2 begins to be charged by the pull-up of the second inverter 12. In consequence of this, the first output Q of the latch 3 is at once forced to a low logic level. The other output Q# will instead take a little longer to change its state because the pull-up transistors of the inverters 11, 12 are highly resistive. Thus, there will be a time period when both said outputs are at a low logic level.
Because of the outputs Q and Q# being connected directly to the respective inputs of a logic gate 13 of the NOR type, the output of the gate 13 will be forced to a high logic level, thereby allowing an NMOS transistor M3 connected to the output node 4 of the circuit 11 to be turned on.
Associated with each address input terminal of the memory circuit is a cell 11, as shown schematically in FIG. 2.
This approach, in the art referred to as the distributed NOR, provides, for each cell, an output connected to a single ATD-LINE line 7 which is usually in the form of a metallization line taken to the supply Vdd through a transistor M4 having its control terminal connected to a ground GND.
An ATD pulse is delivered from this line 7 through an inverter 5.
Each ATD cell 11 can bias the line 7 to ground on the occurrence of an input transition. This line 7 being relatively long, it exhibits resistance and intrinsic capacitance of relatively high values, and if the switching involves all the addresses in parallel, the line 7 will be discharged at a very fast rate; otherwise, when the switching only affects the farthest terminal from the output node, the line 7 is discharged at a slower rate.
Accordingly, this structure has shown to be dependent on the number of addresses being switched. If the switching involves the physically remotest address terminals, then the circuit is subjected to a delay due to the long length of the metal paths. This affects the stability of the ATD pulse duration.
In practice, a different duration of the equalization period is obtained according to which of the terminals has been switched, this having an adverse effect on the memory access time for the read phase.
Thus, the ATD is generated by a transition occurring on at least one of the address input terminals, and it is the signal that will enable the read phase. In ideal conditions of operation, the addresses are either presented to the memory device pins simultaneously, or they are modified with a time interval not shorter than the access time, as illustrated by the graphs in FIG. 3, for example.
Unfortunately, there are no specifications to ensure that the user will take such precautions.
The non-volatile memory device shares a bus 8 of connection to a microprocessor .mu.P with other RAM, A/D, display, etc. peripherals. FIG. 4 shows schematically the connections between the microprocessor and the various peripherals.
When the microprocessor .mu.P is to be communicated to the A/D converter, electric signals are issued or received on the bus 8. Only the signal CE (Chip Enable) is enabled, and in this example, only the signal CE pertaining to the converter, namely the signal CE3#, will be active.
Where the microprocessor is instead to access the flash memory, there is no specification to provide a timing "protocol" for assigning the various signals. Accordingly, the microprocessor will disable A/D and enable the flash memory using the chip enable signals CE1# and CE3#. Thereafter, the microprocessor will begin to send data on the bus 8, but during the time interval between the activation of CE1# and the issuing of the addresses by the microprocessor on the bus, the bus 8 remains charged at the values it had before, and the non-volatile memory will mistake these residual spurious logic values for data addresses and set to work by activating the ATD signal, the timing chain, etc.
In the instance of a fully static memory, that is a memory with no precharged nodes, this is quite straightforward because the stream of signals, from the addresses to the outputs, behaves like a stream of signals in combinational logic. On the other hand, where precharged nodes are provided, proper operation depends on a strict observance of the timing.
Consider, for example, a memory which utilizes a boosted supply to the word line for the read phase. To make full use of the boost effect, this should take place with the word line already at a value close to the supply voltage Vcc.
The boost phase timing is vitally important to the operation of the memory device, and a dedicated timing circuit, shown diagramatically in FIG. 5, is provided specially for this. Each time that an address transition occurs, as revealed by the ATD signal, the circuit executes the decoding of a dummy row located at the edges of the memory matrix and having the same capacitive parameters as the normally used rows.
This operation is effective to sense the time when the voltage of the selected row reaches the value of the supply Vcc. The comparator triggering value is a compromise between the voltage value that can be attained and the time taken to attain it.
If the microprocessor sends out the valid addresses before a previous reading is completed, a new ATD signal is generated. However, the timing chain will still be engaged by the previous reading, and the boost cannot be restarted correctly. In addition, should a second reading be started while the boost capacitor is yet to be recharged to the value of the supply Vcc, a positive result is obtained all the same, but the final boost voltage would be lower and, therefore, the voltage boosted node would be even lower at the end of the second read phase.
In essence, after a few read cycles, the voltage value on the word line will be insufficient to ensure proper operation. It is important, in fact, that several successive readings be verified, rather than a single reading, in order for the repositioning of the nodes to be checked at the end of each phase.
The user is, of course, authorized to change at will and at any time the addresses of the memory locations to be accessed; the last address will be the valid one, that is the address to which the memory device is definitely to output the data, e.g., as shown in FIG. 6. But, since it is impossible to know in advance which address comes last based on current specifications, the device is to be ready at each address transition because any of them could be the last.